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MBM29F800BA-55PF Datasheet (PDF) - SPANSION

MBM29F800BA-55PF Datasheet PDF - SPANSION
Part # MBM29F800BA-55PF
Download  MBM29F800BA-55PF Download

File Size   596.59 Kbytes
Page   49 Pages
Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
Logo SPANSION - SPANSION
Description FLASH MEMORY

MBM29F800BA-55PF Datasheet (PDF)

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MBM29F800BA-55PF Datasheet PDF - SPANSION

Part # MBM29F800BA-55PF
Download  MBM29F800BA-55PF Click to download

File Size   596.59 Kbytes
Page   49 Pages
Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
Logo SPANSION - SPANSION
Description FLASH MEMORY

MBM29F800BA-55PF Datasheet (HTML) - SPANSION

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MBM29F800BA-55PF Product details

■ GENERAL DESCRIPTION

The MBM29F800TA/BA is a 8M-bit, 5.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K words of 16 bits each. The MBM29F800TA/BA is offered in a 48-pin TSOP(1) and 44-pin SOP packages. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. 12.0 V VPP is not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. The standard MBM29LV800TA/BA offers access times 55 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.



■ FEATURES

• Single 5.0 V read, write, and erase

   Minimizes system level power requirements

• Compatible with JEDEC-standard commands

   Uses same software commands as E2PROMs

• Compatible with JEDEC-standard world-wide pinouts

   48-pin TSOP(1) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)

   44-pin SOP (Package suffix: PF)

• Minimum 100,000 write/erase cycles

• High performance

   55 ns maximum access time

• Sector erase architecture

   One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes.

   Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

   T = Top sector

   B = Bottom sector

• Embedded EraseTM* Algorithms

   Automatically pre-programs and erases the chip or any sector

• Embedded ProgramTM* Algorithms

   Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

   Hardware method for detection of program or erase cycle completion

• Low Vcc write inhibit ≤ 3.2 V

• Erase Suspend/Resume

   Suspends the erase operation to allow a read data in another sector within the same device

• Hardware RESET pin

   Resets internal state machine to the read mode

• Sector protection

   Hardware method disables any combination of sectors from write or erase operations

• Temporary sector unprotection

   Temporary sector unprotection via the RESET pin.



 




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