Overview Description
The S1D13700 Embedded Memory Graphics LCD Controller can display both text and graphics on an LCD panel. The S1D13700 allows layered text and graphics, scrolling of the display in any direction, and partitioning of the display into multiple screens. It includes 32K bytes of embedded SRAM display memory which is used to store text, character codes, and bit-mapped graphics. The S1D13700 handles display controller functions including: transferring data from the controlling microprocessor to the buffer memory, reading memory data, converting data to display pixels, and generating timing signals for the LCD panel.

Features
Internal Memory
    • Embedded 32K bytes of SRAM display memory 
Host CPU Interface
    • Direct Address Bus support for:
        • Generic Bus (Z80 family) microprocessor interface
        • MC68K family microprocessor interface
    • Indirect Address Bus support for:
        • Generic Bus (Z80 family) microprocessor interface
        • MC68K family microprocessor interface
        • M6800 family microprocessor interface
    • 8-bit CPU data bus interface
Display Support
    • 4-bit monochrome LCD interface
    • Maximum resolutions supported: 640x240 at 1 bpp 320x240 at 2 bpp 240x160 at 4 bpp
    • 1/2-duty to 1/256-duty LCD drive
Display Modes
    • 1/2/4 bit-per-pixel color depth support
    • Text, graphics and combined text/graphics display modes
    • Three overlapping screens in graphics mode
    • Programmable cursor control
    • Smooth horizontal scrolling of all or part of the display in monochrome mode
    • Smooth vertical scrolling of all or part of the display in all modes
Character Generation
    • 160, 5x7 pixel characters in embedded mask-programmed character generator ROM (CGROM)
    • Up to 64, 8x8 pixel characters in character generator RAM (CGRAM)
    • Up to 256, 8x16 pixel characters in embedded character generator RAM (when CGROM is not used)
Power
    • Software initiated power save mode
    • Low power consumption
    • CORE VDD 3.0 to 3.6 volts
    • IO VDD 3.0 to 5.5 volts
Clock Source
    • Two terminal crystal or Single Oscillator input Input Clock (maximum 60 MHz) FPSHIFT Clock (maximum 15 MHz)
Package
    • TQFP13 - 64-pin Pb-used package
    • TQFP13 - 64-pin Pb-free package (lead free)