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EPM7128AETC100-10 Datasheet (PDF) - Altera Corporation

EPM7128AETC100-10 Datasheet PDF - Altera Corporation
Part # EPM7128AETC100-10
Download  EPM7128AETC100-10 Download

File Size   1007.75 Kbytes
Page   64 Pages
Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation
Description High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX

EPM7128AETC100-10 Datasheet (PDF)

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EPM7128AETC100-10 Datasheet PDF - Altera Corporation

Part # EPM7128AETC100-10
Download  EPM7128AETC100-10 Click to download

File Size   1007.75 Kbytes
Page   64 Pages
Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation
Description High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX

EPM7128AETC100-10 Datasheet (HTML) - Altera Corporation

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EPM7128AETC100-10 Product details

General Description
MAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.

Features...
■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
    – MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532
    – EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532
■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
■ Enhanced ISP features
    – Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)
    – ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)
    – Pull-up resistor on I/O pins during in-system programming
■ Pin-compatible with the popular 5.0-V MAX 7000S devices
■ High-density PLDs ranging from 600 to 10,000 usable gates
■ Extended temperature range
■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), spacesaving FineLine BGATM, and plastic J-lead chip carrier (PLCC) packages
■ Supports hot-socketing in MAX 7000AE devices
■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
■ PCI-compatible
■ Bus-friendly architecture, including programmable slew-rate control
■ Open-drain output option
■ Programmable macrocell registers with individual clear, preset, clock, and clock enable controls
■ Programmable power-up states for macrocell registers in MAX 7000AE devices
■ Programmable power-saving mode for 50% or greater power reduction in each macrocell
■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
■ Programmable security bit for protection of proprietary designs
■ 6 to 10 pin- or logic-driven output enable signals
■ Two global clock signals with optional inversion
■ Enhanced interconnect resources for improved routability
■ Fast input setup times provided by a dedicated path from I/O pin to macrocell registers
■ Programmable output slew-rate control
■ Programmable ground pins




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About Altera Corporation


Altera Corporation was an American manufacturer of programmable logic devices (PLDs), reconfigurable complex digital circuits. It was acquired by Intel Corporation in 2015 and is now a subsidiary of Intel.

Founded in 1983, Altera was one of the pioneers in the field of programmable logic, offering a range of PLD products including field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and specialized chips for digital signal processing and memory interface functions. The company's products were used in a variety of applications including communication systems, industrial automation, medical equipment, and military systems.

Altera was known for its innovation in the PLD market, including the development of high-density FPGAs and low-power, high-performance CPLDs. With its acquisition by Intel, Altera continues to provide PLD solutions for its customers, leveraging the resources and technology of one of the world's largest technology companies.

*This information is for general informational purposes only, we will not be liable for any loss or damage caused by the above information.




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